This application relates to switchable power supplies and, more particularly, to reducing audible noise in power supply transformers resulting from switching power supplies switching in the audible frequency range.
Generally, a typical Quasi Resonant Flyback converter, e.g. converter 100 (FIG. 1A), includes a Quasi resonant pulse width Modulator controller 101 coupled to a transformer 102. Transformer 102 transfers energy directly between its input and output in a single step. Transformer 102 may be used in converting an input alternating current (AC) voltage (Vin) to an isolated output voltage (Vo). The Quasi Resonant Flyback converter 100 also includes a Power MOSFET 104 operating as a switch.
The frequency of a gate signal turning on and off the Power MOSFET is reduced with output load to reduce switching losses. This reduction in frequency is achieved by turning on the Power MOSFET at increasing number of valleys of the drain-source voltage through the sensing of zero-crossing voltage at ZC pin. The zero crossing voltage signal is derived from the output voltage of an auxiliary winding (indicated by signal designation “Wa” in FIG. 1) in Quasi Resonant Flyback converter 100 in the power supply. In order to ensure correct zero crossing monitoring, during a period of time starting from the instant the gate of transistor 104 is turned off, converter 100 is normally prevented from detecting any zero crossing voltages to reject any ringing at a zero crossing pin of transistor 104. However due to tolerances, the actual timing may fluctuate and an unwanted disturbance to the system may result.
For example, audio noise is generated in the transformer 102 when there is a low frequency jittering due to variations in untrimmed ringing suppression times, maximum on and off time and maximum switching periods. Any switching frequency lower than 20 KHz, e.g. a switching period which is greater than 50 μs, would induce audible noise. The audible noise that due to the maximum switching period is not limited or, not accurate even it's being limited.
Another issue is that if the ringing suppression time, maximum on and off time and maximum switching period change in different directions, thereby affecting the input power. For example, if the ringing suppression time becomes larger while the maximum switching period becomes smaller, a maximum duty cycle will be reduced. As a result, the system might not be able to meet its output load requirements.
Although these timing may be trimmed, these inaccuracies of the ringing suppression time, maximum on and off time and maximum switching period can result in gate switching in the audible frequency range. If the timing is to be trimmed individually, this will require a large die area for converter 100 which is undesirable.
Certain known techniques include using an analog mode control to suppress untrimmed ringing times. The suppression time is generated by a comparator and a capacitor charging block with two charging current path options. The comparator compares the zero crossing voltage to a threshold voltage. If the zero crossing voltage is greater than the threshold voltage, a higher charging current path is chosen to charge the capacitor. Hence the ringing suppression time is small when the zero crossing voltage is high. If the zero crossing voltage is less than the threshold voltage, a smaller charging current path may be chosen to charge the capacitor. Hence the ringing suppression time is large when the zero crossing voltage is low.
One drawback of known methods is illustrated in FIG. 1B. In FIG. 1B there is shown a timing diagram 150 that illustrates a slope 152 of the voltage of a capacitor (not shown) that is used to set the ringing suppression time for the switching power supply. Timing diagram 150 illustrates zero crossing voltage 154, the voltage 158 and 160 of the charging capacitor and the gate signal 162. The slope 152 is determined using the charging current and capacitor as mentioned before. When the zero crossing voltage 154 is less than a threshold value 164, e.g. 0.7 V, the capacitor is charged by smaller current in order to achieve a longer ringing suppression time (e.g. Slope 158), however, when the zero crossing voltage crosses over the threshold, the slope will be changed as a larger charging current path is selected in order to achieve a smaller ringing suppression time (e.g., Slope 160). Ideally, the ringing suppression time would be the time that the voltage of line 170 is less than a predetermined voltage 172, e.g. 2.0 V. However with using current known techniques, the ringing suppression time will be longer than required, which may result in a longer ringing suppression time that could affect the feedback loop in the whole system.